Various electronic applications and chip packages may include more than one semiconductor chip. Such applications may include a leadframe, which may carry a chip such as a power semiconductor chip, and it may be necessary that a further chip, e.g. a controller chip may be electrically isolated from the leadframe. Chip adhesion materials, which may be used for electrical insulation, and which may include electrically insulating materials, e.g. an electrically insulating glue, may possess some required general thermomechanical mechanical properties, however they may not exhibit sufficient heat dissipation to enable sufficiently large losses of heat to be removed from the electronic circuit. It is desirable for heat to be dissipated efficiently from the chips and away from the lead frame. Other desirable characteristics which are not being met by current techniques include being able to place precisely, electrically insulating isolation islands on the leadframe. It is further desirable to reduce processing costs.
Up until now, as shown in FIGS. 1A and 1B, logic chips and power chips may be connected to a leadframe. For example, a logic chip 101, shown in FIG. 1A as top chip, may be formed over a power chip 103, when connecting logic chips over a lead frame 105 in a housing. This arrangement may apply, for example, to a Cool MOS chip in a TO-220 housing. An isodrain 107, e.g. a metal (Cu)-ceramic-metal (Cu) sandwich, also called a double copper bonding (DCB) layer may be arranged between the chip, e.g. between power chip and the leadframe as shown in FIG. 1B.
FIGS. 2A to 2C show a chip-by-chip arrangement and an isodrain 107 (DCB) with an isolated power chip. FIGS. 2A and 2B show top views of a logic chip 101 disposed over a power chip 103 in an integrated circuit. FIG. 2C shows a side view of a realized DCB 107 between the power chip 103 and lead frame 105. Realization of the DCB metal-ceramic-metal sandwich may include complicated and expensive processes. One of the highest costs factors of the DCB is the double soft soldering process for the ceramic process, and even the connection of the ceramic to the chip back side. Furthermore, the design modifications adapted for each chip-dimension are lengthy and expensive.